1. Field of the Invention
The present invention relates to an integrated circuit test system for testing operations of LSIs (large scale integrated circuits) and the like.
2. Description of the Prior Art
With recent increase in size of LSIs, the amount of test pattern data used for testing an LSI has been increased. The increase in test pattern data amount tends to cause a problem in which test pattern data can not be stored in a pattern data memory. In such a case, the capacity of the pattern data memory can be increased. However, increasing the pattern data memory capacity results in increase in costs and also there is a limit for an increase amount. Moreover, if the amount of test pattern data is increased, an increased time is required for loading the test pattern data onto a pattern data memory is increased, so that a time required for setting up a tester (integrated circuit test system) is unexpectedly increased.
A technique for compressing test pattern data and storing the compressed test pattern data has been well known (see, for example, U.S. Pat. No. 6,661,839B1). More specifically, for example, as described in FIG. 109 of U.S. Pat. No. 6,661,839B1, an expansion system for expanding the compressed data at high speed in parallel to each pin is provided and, based on data expanded data by the expansion system, a test signal is sent to a semiconductor integrated circuit.
However, providing the expansion system might cause increase in circuit size and fabrication costs. This problem becomes more apparent, for example, when plural kinds of compression/expansion algorithms are used as shown in FIG. 43 of U.S. Pat. No. 6,661,839B1. Furthermore, it is difficult to compress/expand by a new algorithm and there is also the problem of lack of flexibility.